TI, Mixed Signal Verification (1-2Years)

Job Opening: AMS Design Verification Engineer

Qualifications:

• 1-2 years of experience in Analog Mixed-Signal (AMS) design verification.
• Proficient in developing Verilog, Verilog-A, or Verilog-AMS models for signal and power management modules.
• Experience with full chip design verification is a plus.
• Ability to create and manage Full-Chip AMS-DV plans and implement best practices.
• Strong debugging skills and experience with analog power IPs to resolve chip-level AMS issues.
• Familiarity with tools like Cadence Virtuoso, Spectre, and AMS simulators.
• Knowledge of RTL and Gates+SDF for back-annotated timing simulations, including analyzing parasitic effects.
• Experience with constrained-random stimulus and auto-checking verification environments.
• Capable of working independently in a fast-paced environment and collaborating with design teams to track and resolve bugs.

Apply Here

https://www.linkedin.com/in/kathir-balakrishnan-05a4472b/